Method of making a silicon on insulator wafer

ABSTRACT

A process for making silicon on insulator wafer by bond and etch back—BESOI. A boron etch stop is formed by BF2+ ion implantation followed by solid phase epitaxy—SPE. Fluorine getters metals for OISF immunity of the final wafer. SPE activates boron above solubility limit thus facilitates high etch selectivity. Future cap silicon film is epitaxially grown over the boron etch stop at temperature that limits boron diffusion and boron deactivation. High temperature hydrogen bake step in epitaxy is replaced with Siconi of similar low temperature process. Buried oxide is thermally grown from portion of cap silicon layer at temperature limiting Boron diffusion and deactivation. Thus, SOI wafer design is the same as in layer transfer process—bonding interface is at the bottom interface of BOX; properties of final SOI wafer are equal to SOI made by layer transfer process—including cap silicon layer thickness variation, and OISF defect count. Advantage over the layer transfer—this process does not require non-standard equipment. Standard processing tool set readily available at semiconductor foundries is sufficient to run this process. Foundries can use this process for in house SOI wafer manufacturing.

REFERENCE TO RELATED APPLICATIONS

This application claims an invention which was disclosed in ProvisionalApplication No. 63/008,795, filed Apr. 12, 2020, entitled “Method ofMaking Silicon-on-insulator Wafer”. The benefit under 35 USC § 119(e) ofthe United States provisional application is hereby claimed, and theaforementioned application is hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION Field of the Invention

The invention relates to methods of making silicon on insulator wafersthat can be further used for making chips, which can be further used invarious electronics as smartphones or computers.

Description of Related Art

Semiconductor technology is making integrated circuits, also calledchips. Mainstream is making them on bulk silicon substrates calledwafers. The chip consists of an array of transistors or othersemiconductor devices. Each transistor must be electrically insulatedfrom neighboring devices in the semiconductor body. Either bulk siliconwafers or silicon on insulator—SOI—wafers can be used as a startingmaterial in the chip production. For SOI, insulation of individualtransistors from each other is simpler compared to bulk Si: transistorbottoms are already insulated, so only sides must be insulated.Eventually the chip manufacturing from SOI wafer is simpler and finalchip have better performance compared to the bulk-made chips and canhave more functions. For example, the chips on SOI can contain bothanalog and digital circuitry, thus, say, a front-end chips of cellphones are now made from SOI wafer.

SOI wafers can be made various ways. Initially, in 1960s it wassilicon-on-sapphire—SOS—technology. Later other methods weredeveloped—SIPOS, ZMR, SIMOX, BESOI, Eltran, Smart-Cut, etc., seeColinge, J-P. Silicon-on-insulator technology: materials to VLSI.Springer, 2004. Currently, only layer transfer (Smart-Cut) process isused to make mainstream chips. BESOI (Bond-and-Etch-back SOI) process isused for thick SOI—in niche applications as MEMS. All other processesare abandoned now as being inferior to the layer transfer process.

BESOI wafers are currently manufactured in high volume using single etchstop technology, see Tilli, Markku, Mervi Paulasto-Krockel, TeruakiMotooka, and Veikko Lindroos, eds. Handbook of silicon-based MEMSmaterials and technologies. William Andrew, 2015. The one-etch-stopprocess limits manufacturing to thick SOI only. Thick is SOI with capsilicon layer about 1 micron or thicker. These are SOI for MEMSchips—microphones in cell phones, acceleration sensors for vehicleairbags, jet printer heads, etc. These are mostly discrete devices.Currently no thin BESOI process in commercial use.

The BESOI process was initially developed by IBM in mid 1980s.—J. Lasky,Wafer bonding for silicon on insulator technologies, Appl. Phys. Lett.48 (1986) 78. Later this process has been abandoned by IBM, and by therest of industry. The major problem is high defect density in the topsilicon film. It is an OISF type defect—oxidation induced stackingfault—Maszara, W. P., P. P. Pronko, and A. W. McCormick. “Epi-lessbond-and-etch-back silicon-on-insulator by MeV ion implantation.”Applied Physics Letters 58, no. 24 (1991): 2779-2781.

The OISF defects are formed when there are nucleation centers and a fluxof interstitials. A typical nucleation center is a metal contaminationin Si. Oxidation of silicon generate interstitials at growing Si—SiO2interface. During oxidation incoming interstitials sequentially attachto the nucleation center and form OISF rings. The rings might have up tomicron size. The bigger defect size is, the higher probability that itwill become a killer defect. OISF is usually a killer. The OISF duringCMOS chipmaking process causes GOI—gate oxide integrity failure. Thus,the final chip fails.

BESOI process inevitably includes BEOL (back of the line) steps. Forexample, it includes grinding of device wafer. BEOL is heavily metalcontaminating. Say, during the grinding, iron, nickel and othercontaminants from grinding wheels diffuse through the device wafertoward Si-BOX interface. They become nucleation centers for the OISF.High OISF count in BESOI wafers causes low yield for chips made fromthese wafers. This was the major reason why semiconductor industryabandoned BESOI process in early 1990s.

Layer transfer (Smart-Cut) process uses FEOL (front of the line)processing steps only. FEOL is essentially metal free. Therefore, thereis no starting point for the OISF grow, and the final SOI wafers areOISF free.

Another difference between BESOI and Smart-Cut wafers is location of thewafer bonding interface. In BESOI the interface is at top side of theBOX, while in Smart-Cut it is at bottom of the BOX. Bonding interfacehas many types of defects, structural and electrically active ones. InBESOI the bonding interface is closer to transistors, therefore it oftencauses yield drop. Art would benefit from BESOI process resulting inbonding interface at bottom of BOX side, thus having low defect densityat the more important top Si-BOX interface, like in Smart-Cut.

Still, the layer transfer process of making SOI has disadvantages. Forexample, it needs special equipment and non-standard equipment. Thespecial tool required is a high dose hydrogen and helium ion implanter.The non-standard (not commercially available) is the wafer cleave tool(after implant and bond). Art would benefit from a method of making thinSOI wafers that requires only standard equipment readily available atsemiconductor foundries. Thus foundries will be able to manufacture SOIwafers in-house.

SUMMARY OF THE INVENTION

New process flow is used for growing a layer stack on the device wafer:

ion implantation of BF2+ species into p− epi laying on p+ startingsubstrate,

anneal at 450-580 C after the implant step,

surface preparation for epitaxy using low temperature process,

epitaxy of silicon layer at temperature below 800 C,

thermal oxidation at temperature below 800 C

anneal at 350-750 C after removal of p− layer, before removal of boronetch stop layer

finalizing of wafer bonding by anneal.

The BF2 implantation is for

amorphize buried layer in Si—to facilitate further boron activation withSPE

dope with boron—to form 2^(nd) etch stop

dope with fluorine—to provide metal getter thus further suppress OISFdefects

dope with fluorine—to lower interface state density at BOX—Si interfaces

The post implant 450-580 C anneal is for

epitaxially regrow previously amorphized layer—to enable next epitaxy ofcap silicon

to electrically activate the implanted boron, thus enable furtherselective etching

minimize boron out diffusion from implanted peak, thus enable highselectivity etch

lower fluorine losses—to keep fluorine capacity further serving as metalgetter.

The surface preparation for epitaxy is for

removal of native oxide—same function as hydrogen bake, but at lowtemperature —thus no autodoping of cap Si by Boron diffusion fromimplanted layer

performed in Siconi chamber of Centura tool, or similar function Previumchambers in Intrepid/Epsilon tools

The epitaxy step is for

grow a silicon layer that will ultimately become a cap silicon layer infinal SOI wafer

use low temperature<800 C—to keep low enough boron autodoping from theetch stop layer

The thermal oxidation step is for

grow a dielectric layer that will ultimately become a BOX in final SOIwafer

enable wafer design with wafer bonding interface at bottom interface ofBOX; this eventually provide better GOI and better electricalperformance of chips made on the SOI

use low temperature<800 C—to keep boron autodoping from etch stop layerlow

anneal at 350-750 C before removal of boron etch stop layer is for

getter metals from cap silicon by layer with heavy B and F content—thusfor eventual OISF suppression.

The bond finalizing step is for

achieve mechanical property of the bonding interface equal to bulk SiO2

achieve good electrical properties of the interface, i.e., low interfacestates density.

Summarizing—BESOI process includes preparation of device and handlewafers, bonding them and thinning the device wafer. The device wafermaking includes new steps:

(a) Simultaneously amorphize, dope, and modify silicon layer(b) Simultaneously epitaxially regrow previously amorphized layer andactivate dopant(c) Low temperature bake off native oxide to enable epitaxy of futurecap Si layer while excluding autodoping of the cap Si with Boron frometch stop layer.

Novelty—Si:B:F layer is used for BESOI fabrication for the first time:

(a) use of Si:B:F layer as 2^(nd) etch stop,(b) Si:B:F is made by ion implantation followed by solid phase epitaxy(SPE),(c) at cap Si epi step, H bake is replaced with low temperature process(d) after bonding, grinding, and 1^(st) etch stop removal steps, beforeSi:B:F layer etch, a metal gettering anneal is performed,(e) BOX is grown on device stack, not on handle stack.

BESOI processes known in the art use either SiGe or Si:B as 2^(nd) etchstops, see review—Maszara, W. P. “Silicon-On-Insulator by Wafer Bonding:A Review.” Journal of the Electrochemical Society 138, no. 1 (1991):341. Compared to known SiGe based process, FIG. 2, FIG. 3 thisdisclosure (a) allows higher quality SOI (lower defect count wafers),(b) OISFs, etch pits, slips, threading dislocations are suppressed, (c)lower cost, (d) fully FEOL compatible, (e) device wafer stack is stableenough to grow thermal BOX on it; thus wafer design improves—bondinginterface is now spaced away from active (where transistors will beformed) cap Si layer; finally chip yield and chip electrical performanceimproves.

Referring to FIG. 2—in known process, SiGe does not allow growingthermal oxide on cap Si (as SiGe relaxes at oxidation temperatures).Therefore, old process uses BOX grown on handle stack. Thus, final SOIget bonding interface at undesirable location—on top of BOX. Electricalproperties of final SOI thus compromised. In new process, device waferstack has more thermally stable Si:B:F layer. Thus, BOX can be thermallygrown. Oxidation temperature must be 800 C or less—to limit Borondiffusion into cap Si. Referring to FIG. 3—in known process, highlystrained SiGe layer is prone to relaxation (i.e., form defects)especially near wafer edges. KLA SP2 haze maps typically show high haze(relaxed SiGe) near wafer edges. Quality of final SOI thus compromised.In new process, Si:B:F has much lower stress than SiGe. Therefore Si:B:Fdoes not develop defects while SOI wafer is manufactured. Quality offinal SOI thus improved.

As compared to Si:B based process known in the art FIG. 4, FIG. 5, thinSOI enabled for the first time. Inventive Si:B BESOI process is comparedto a process described in a paper Maszara, W. P., Goetz Goetz, A.Caviglia, and J. B. McKitterick. “Bonding of silicon wafers forsilicon-on-insulator.” Journal of Applied Physics 64, no. 10 (1988):4943-4950.

Referring to FIG. 4—in old process, native oxide bake-off done at hightemperature>1000 C, typically 1150 C. Therefore, Boron diffuses frometch stop layer into p− layer. After outdiffusion, less than 1E20 cm-3boron left in Si:B. It further causes low etch selectivity; processfails. In new process, Hydrogen bake replaced by low temperature oxideremoval—in situ Centura-Siconi or Entrepid-Previum. Thus in inventiveprocess neither cap Si nor Si:B suffer from Boron diffusion. Eventuallythin SOI process enabled. Referring to FIG. 5—in old process, Boronconcentration is limited to solid solubility. For efficient etch stop, Bhas to be 1E20 cm-3 or higher. It further requires temperature>1150 C.At >1150 C B diffusion prevents making thin SOI. In new process, foretch stop, B has to be electrically active. It is done byamorphization-SPE sequence at <600 C, thus B diffusion is negligible.SPE is not limited to solubility limit, thus >1E20 cm-3 easily obtained,giving high >100:1 etch selectivity.

Notice, when thin BESOI technology was in existence—from mid 80s tillmid 90s, the low temperature alternative to hydrogen bake was not knownyet. Now BF2/SPE/Siconi sequence being patented here—allows thin BESOI.

Final wafer has the same design—“BOX-bottom-bonding+thermal oxide BOX”as wafer made by layer transfer—Smart-Cut. Therefore, this BESOI waferis equal in quality to layer-transfer-made one.

Fluorine content from BF2 implant: passivates traps near thegate-dielectric interface resulting in lower leakages in final chips.Low leakage is a footprint of disclosed process on final product—SOIwafer. Other footprints are—fluorine near cap Si-BOX interface, and lowOISF count/high GOI yield.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 illustrates a schematic process flow of BESOI process due to theinvention.

FIG. 2 compares art process with SiGe etch stop (left) to inventiveprocess (right).

FIG. 3 further compares art process with SiGe etch stop to inventiveprocess

FIG. 4 compares art process with Si:B etch stop to inventive process

FIG. 5 further compares art process with Si:B etch stop to inventiveprocess

FIG. 6 shows as-implanted boron profile after exemplary implant recipeBF2+ at 55 keV, 9E14 cm-2.

FIG. 7 illustrates concept of SPE process.

FIG. 8 schematically show device and handle wafer stacks before waferbonding step for RF SOI.

FIG. 9 schematically show a device wafer stack obtained by inventiveprocess.

FIG. 10 illustrates boron profile widening for exemplary 750 C oxidationused to manufacture device wafer stack

FIG. 11 illustrates boron profile widening for exemplary 800 C oxidationused to manufacture device wafer stack.

DETAILED DESCRIPTION OF THE INVENTION 1^(st) Preferred Embodiment

First, a seed wafer is prepared. It can be called also donor wafer, ordevice wafer. Starting wafer is, for example an epi wafer 300 mm sizehaving p++ bulk and 1 to 5-micron thick p− epi. Wafers with 5-micron epiare readily available from all major wafer manufacturers as they areused in mainstream CMOS chip manufacturing. The 5-micron thickness isacceptable, but not optimal for the inventive process. An optimal1-2-micron epi can be made either on special order or grown in-house.Referring to FIG. 1, step 1, BF2+ ion implantation is performed into thep− epi. An exemplary recipe—implant at 55 keV, 9E14 cm-2—satisfies allthe conditions needed: (1) it amorphizes Si from surface to about 100nm, (2) deliver proper amount of Boron to form high selectivity etchstop, (3) deliver Fluorine—to exclude OISF formation during chipfabrication. For the BESOI process, an obvious method to prevent OISF—bylowering of metal contamination—is not applicable—as there are BEOLsteps in the process—grinding of sacrificial wafer, HNA etching till1^(st) etch stop, etc. In this invention the metal contamination problemis solved by an metal gettering by layer that is heavy doped Boron andFluorine. This provides OISF immunity.

An exemplary recipe 55 keV, 9E14 cm-2 can be done at medium or highcurrent implanters available at fabs, for example AMAT (Varian) HCimplanter. In this recipe Boron has energy 12.35 keV. FIG. 6 shows anas-implanted boron distribution: —concentration for etch stop->2E19 cm-3is from 12 till 78 nm, peak concentration 9.6E19 provides high enoughselectivity >100. Optionally the wafer can be oxidized—10 nm SiO2—beforeimplant—to avoid channeling, and for easy post implant clean by oxidestrip.

Energy range for BF2+ implant—10-100 keV. At lower energy much higherdose is needed to exceed amorphization threshold. At higher energy boronpeak is too wide and deep thus thin SOI is more difficult to form.

Dose range for BF2+ implant—5E14-5E15 cm-2. At lower doses amorphizationdoes not happen—thus no SPE, no B activation, no etch stop. At higherdoses F and B clusters are formed, further causing defects in capsilicon.

Referring to FIG. 1, step 2, solid phase epitaxy (SPE) is performed. SPEis a special mode of recrystallization of amorphous layer if it is incontact with a crystalline lattice, see FIG. 7 for illustration.Amorphous Si itself is stable till 600 C. Above 600, crystals nucleatein bulk of a-Si and grow until all becomes crystal grains (polycrystal). At temperatures 450-580 C there is no nucleation in bulk ofa-Si. Amorphous Si only crystallize at a/c interface inheriting properlattice orientation and lattice constant. The a/c interface moves tillall a-Si becomes single crystal.

Surprisingly, despite almost any ion implanter has BF2+ capability, BF2+followed by SPE is still not well studied, see Mirabella, S., G.Impellizzeri, E. Bruno, L. Romano, M. G. Grimaldi, F. Priolo, E.Napolitani, and A. Camera. “Fluorine segregation and incorporationduring solid-phase epitaxy of Si.” Applied Physics Letters 86, no. 12(2005): 121905. Even though, fluorine redistribution upon SPE has brightanomalous feature—heavy segregation toward surface, still no muchstudies beyond University of Padova, Italy team. In this application,the fluorine segregation toward surface is very advantageous—we get (1)high F concentrations near bottom of cap Si in final SOI wafer—thisgives OISF suppression as F prevents metal precipitates to evolve intoOISF, (2) high F content in BOX—as BOX is grown here. —all excess offluorine “self-removes”—leave wafer after SPE. Thus, only less than few% of as-implanted fluorine is left in silicon. Upon next anneal steps inBESOI processing, this fluorine redistributes by diffusion andeventually binds to existing defects in cap Si and Si-BOX interface thuspassivating them.

So far, only one commercially viable application of BF2/SPE isknown—making shallow source/drain contacts in MOSFETs—Kanemoto, Kei,Akira Nakada, and Tadahiro Ohmi. “Minimization of BF2+-Implantation Doseto Reduce the Annealing Time for Ultra-Shallow Source/Drain JunctionFormation below 600° C.” Japanese journal of applied physics 37, no. 3S(1998): 1166. To the best of our knowledge, it was no attempts to useBF2-then-SPE to make BESOI in the art.

The higher temperature, the higher SPE rate. We need to SPE 50-100 nm oflayer amorphized by implantation in reasonable time range—10-100minutes. 100 nm of pure Si will SPE in ˜10s at 580 C and in ˜10 min at450 C. B-doped Si SPE rate is roughly 10× faster than pure. F-doped SiSPE roughly 100× slower than pure. Finally, B+F doped Si SPE roughly 10×slower than pure. Therefore, the temperature range for SPE is 450-580 C.At lower temperatures SPE is too slow. Above 580 C SPE regrown layercontains defects. Optimal temperature/time is around 550/30 min. ThisBF2/SPE process is somehow like making shallow source/drain extensionswhich also calls for amorphization/SPE to get electrically active Boronwell above solubility limit.

An important feature of SPE—activation well above solubility limit—isused here. SPE is performed at low temperature<600 C, thus it is anideal to prevent undesirable Boron diffusion. Notice, Si:B:F layerbehavior was neither well studied/understood, nor used to improve BESOIprocess.

There were attempts in the art as to make BESOI wafer using BF2 ionimplantation—see: Desmond, Cynthia A., Charles E. Hunt, and Shari N.Farrens. “The Effects of Process-Induced Defects on the ChemicalSelectivity of Highly Doped Boron Etch Stops in Silicon.” Journal of TheElectrochemical Society 141, no. 1 (1994): 178-184. However, they usedRTA (rapid thermal anneal), not SPE. Thus, no high boron activation,then no good etch selectivity, heavy boron out diffusion, and eventuallylow quality BESOI wafer.

Referring to FIG. 1 step 3, the wafer is loaded into epitaxy tool—togrow cap silicon film over the boron etch stop layer. Regular epi cannotbe used—it starts from hydrogen bake step at >1100 C. At thistemperature boron diffuses and B concentration in ion implant peakdrops. If it drops below 2E19 cm-3, the layer will not serve as an etchstop anymore. Also, above 800 C “over-solubility-limit” boronde-activates, thus does not contribute to the etch selectivity.Therefore, traditional hydrogen bake cannot be used here. Instead, lowtemperature process is used to prepare surface for epitaxy—i.e., removenative oxide from surface. If AMAT tool is used, the surface preparationis done in Siconi chamber—before wafer moves into epi chamber. If ASMEpsilon or Intrepid tool is used, the surface preparation is in Previumchamber. Even though Siconi and Previum are different processes, for ourpurposes important is only that they both capable to remove native oxidefrom surface at low temperature, thus enabling epitaxy.

Referring to FIG. 1, step 4, regular silicon epitaxy is performed attemperature 800 C or below. 800 C limit is for the same reasons—limitboron diffusion and prevent boron deactivation. As cap silicon istypically thinner than 100 nm, this limitation does not lower thethroughput. Regular deposition from trichlororosilane takes about 100 s.

All other steps of BESOI wafer manufacturing—bonding and thinning—arethe same as in a regular process known in the art, therefore these stepsare not described here.

2nd Preferred Embodiment

This embodiment describes how to enable proximity metal gettering atfinal stages of SOI wafer fabrication. Thus, metal contamination fromall process steps that are before the final thinning does not cause OISFand next GOI failure in the chips. For BESOI manufacturing it means thatBEOL lines can be used, except 3 final process steps—boron etch-stopremoval, bond finalizing, and cap silicon layer thickness adjustment.

An issue inherent to all SOI wafers regardless of manufacturing method(SIMOX, BESOI or layer transfer) is that BOX precludes metal getteringby handle wafer from cap Si. Therefore, BESOI wafers made with theprocesses known in the art are extremely sensitive to metalcontamination. This disclosure enables gettering in BESOI thussuppressing OISFs, improve GOI and yield of final chips.

Here, the Si:B:F layer serves as the getter instead of the substrate. InSi, almost any heavy doped region has gettering activity, B+F doped isnot an exception. Thus, Si:B:F serves 3 functions—template for cap Siepi, etch stop, and getter. The metal gettering is performed byannealing of SOI wafer after selective etch away of p− layer and beforeselective etch of Si:B:F layer. Anneal is in temperature range—350-750C. At temperatures below 350 C gettering loses efficiency (due tolowering diffusivity of metals in Si with temperature). At temperaturesabove 750 C boron start diffusing into cap Si layer. One skilled in theart can choose the proper annealing temperature to achieve efficientgettering using, for example, using a textbook by Geng, Hwaiyu.Semiconductor manufacturing handbook. 2^(nd) edition, 2017, chapter3.4.2.

F in Si is also known as an efficient metal getter, thus BF2 implantmaximizes gettering efficiency. The etch stop Si:B:F layer issacrificial, thus all gettered metals are removed together with thesacrificial layer.

3^(rd) Preferred Embodiment

In this embodiment an oxidation step added at the end of making thedevice wafer stack.

This way the design of the final wafer changes—bonding interface is atBOX bottom, not on top. And, BESOI turns the same design as layertransfer wafer. Accordingly, all advantages of this design (1) BOX—capSi interface has automatically zero particles (2) less flakes and otherbonding-related defects, (3) lower interface state density at BOX—cap Siinterface=better electrical performance of final chips.

During oxidation some boron diffusion from p+ layer into cap Si willhappen. Still, there is a process window where the B diffusion isacceptably low—at 750-800 C. Boron diffuses by vacancy jump mechanism.Therefore, the diffusion coefficient drops exponentially withtemperature: 3E-13 at 1100 C and 5E-17 at 800 C; Lowering temperature by300 C—from 1100 down to 800 C—results in 4 orders of magnitude drop ofdiffusion coefficient—see FIG. 10a —from Jones, Scotten W. “Diffusion insilicon.” IC Knowledge LLC (2008): p. 25. Therefore, loweringtemperature is extremely efficient way to control and minimize Bdiffusion.

Typical BOX thickness is 200 nm. At 750 C it needs 13 hours to grow, at800 C—it needs 6 hours (reasonable), see FIG. 10, FIG. 11. Anotherreason to limit temperature—risk of B deactivation (remember, we have Bwell over solid solubility limit). The deactivation means dropping etchselectivity, which is undesirable. At 800 C and below there is no anysignificant deactivation. Also, the universal trend (i.e., Moore's law)in semiconductor industry is size shrinking. Thus, for next generationsof SOI wafers—having thinner BOX around 20 nm, 750 C oxidation will takemuch shorter time.

Referring to FIG. 10—an example of calculations: Oxidation temperature750 C. To get final 80 nm cap Si SOI—add 88 nm—to be consumed byoxidation and add 28 nm to compensate B diffusion into cap Si duringoxidation, add 4 nm to compensate B diffusion while epi of cap Si. Totalepi needed: 80+88+28+4=200 nm.

Referring to FIG. 11—if oxidation temperature is 800 C. To get final 80nm cap Si SOI—add 88 nm—to be consumed by oxidation, add 60 nm tocompensate B diffusion into cap Si during oxidation, add 4 nm tocompensate B diffusion while epi of cap Si. Total epi 80+88+60+4=232 nm.

4^(th) Preferred Embodiment

This embodiment is for making RF SOI. RF SOI wafer has an additionallayer—polysilicon. BESOI process known in the art grow BOX from top ofhandle wafer stack. For RF SOI case, there is poly layer on the top ofthe handle stack. Thus, in known processes, BOX is made by oxidizingpolysilicon. This inevitably forms very rough interface between poly andBOX.

In the inventive process, BOX is grown on device wafer stack, not onhandle stack. Therefore, no rough BOX/poly interface in final SOI wafer.FIG. 8 illustrates device wafer stack and handle wafer stack beforebonding and thinning.

5^(th) Preferred Embodiment

In this embodiment, 2 separate ion implants done instead of single BF2+or single BF3+ implant. One is boron implant; another is fluorineimplant.

Boron implant is at 5 to 20 keV—to get proper dopant location. However,boron is a light ion, thus it does not cause amorphization ifimplantation done at room temperature. B+ must be implanted into wafercooled below about −50 C to achieve amorphization. End stations withcooling are available on many implanters, thus no technical challengehere. Alternatively, F+ implant can be used for amorphization. Though F+ion beam current is typically significantly lower than for BF2+ specie,so throughput will suffer. Advantages of separate B and F implants isthat energy and dose of each specie can be independently optimizedachieving high etch selectivity by Boron implant/SPE optimization, andefficient OISF suppression as well as lowering of wafer bondingtemperature by F implant optimization. With separate F implant, fluorinecan be implanted later, after BOX grown on device stack wafer, rightbefore bonding. This allow F placement at future BOX/cap Si interface,thus maximizing F efficiency for suppression of OISF. This option isdescribed in co-pending application by author.

In Silicon lattice, Boron has vacancy diffusion mechanism, whileFluorine has interstitial diffusion. Therefore, Fluorine diffusion isfaster and proceeds at lower temperatures compared to Boron. To keepFluorine from out diffusion and get maximum of its positive effects onOISF reduction, and on wafer bonding, all the following is useful (1)implant it later in the process flow, (2) use low 550 C or lowerprocessing temperatures, (3) have oxide on surface before implant tocapture F.

1. A method for making silicon on insulator wafers comprising;preparation of device and handle wafers where said device wafercomprises a sacrificial starting wafer covered with a stack of layers,said stack comprises etch stop layers, future cap silicon layer, andfuture BOX layer, said etch stop layers comprises 1^(st) and 2^(nd) etchstop layers where said 1^(st) etch stop layer comprises low dopedsilicon epi layer over heavily doped said sacrificial bulk wafer, said2^(nd) etch stop layer comprises heavily boron doped layer, bonding ofsaid device wafer stack to said handle wafer, preparing bonded waferassembly for thinning by anneal step, thinning of said device waferstack by complete removal of said starting wafer by sequence of grindingand HNA etching, and removal of etch stop layers until said cap siliconfilm exposed characterized in that said 2^(nd) etch stop layer is formedby a sequence of ion implantation and solid phase epitaxy, and said ionimplantation uses Boron and Fluorine containing species, and said Boronconcentration in said 2^(nd) etch stop layer is equal or exceeds 1E20cm-3, and said concentration of Boron is achieved by solid phase epitaxyof layer amorphized by said ion implantation said cap silicon layer isgrown over said 2^(nd) etch stop layer by epitaxy after surfacepreparation at low temperature.
 2. The method of claim 1, where said ionimplantation comprises implanting FB₂+ ion species.
 3. The method ofclaim 2, where said implantation dose is chosen to cause amorphizationof silicon from surface to a depth defined by implant energy.
 4. Themethod of claim 3, where energy of said ions is in a range from 20 to100 keV.
 5. The method of claim 3, where dose of said ions is in a rangefrom 5E¹⁴ to 5E¹⁵ cm⁻².
 6. The method of claim 2, where said boron etchstop layer is formed by electrical activation of implanted boron withsolid phase epitaxy.
 7. The method of claim 6, where where said solidphase epitaxy is performed by <1° C./minute ramp up anneal starting from450° C. till 600° C.
 8. The method of claim 1, where said cap siliconlayer is grown over said 2^(nd) etch stop layer by epitaxy after surfacepreparation for epi at temperature below 600° C.
 9. The method of claim8, where said epitaxy of the cap silicon layer is performed attemperature equal or below 800° C.
 10. The method of claim 9, where saidburied oxide layer is grown from portion of said cap silicon by thermaloxidation at temperature equal or below 800° C.
 11. The method of claim1, where gettering anneal at 350-750° C. is performed after grinding andHNA etching steps of said bonded device stack and handle wafers.